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rev.1.00, may . 24. 2007, page 1 of 12 r1lv0414d series 4m sram (256-kword 16-bit) rej03c0312-0100 rev.1.00 may.24.2007 description the r 1 lv0414d i s a 4-m b i t st at i c r a m organi zed 256-kword 16-bi t , fabri cat ed by r e nesas?s hi gh-perform ance 0.15 m c m os and tft t echnol ogi es. r 1 lv0414dseri es has real i zed hi gher densi t y , hi gher perform ance and l o w power consum pt i on. the r 1 lv0414d seri es offers l o w power st andby power di ssi pat i on; t h erefore, i t i s sui t a bl e for bat t e ry backup sy st em s. it has packaged i n 44-pi n tsop ii. features ? si ngl e 3.0 v suppl y : 2.7 v t o 3.6 v ? fast access tim e: 55/70 ns (m ax) ? power di ssi pat i on: ? st andby : 3 w (ty p ) (v cc = 3.0 v) ? equal access and cycle tim es ? c o m m on dat a i nput and out put . ? three state output ? b a t t e ry backup operat i on. ? tem p erat ure range: -40 t o +85 c ordering information t y p e no . a ccess time packag e R1LV0414DSB-5SI 55 ns 400-mil 44-pin plastic t s op ii (44p3w -h) r 1 l v 0 4 1 4 d s b - 7 l i 7 0 n s
r1lv0414d series pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs# i/o0 i/o1 i/o2 i/o3 v v i/o4 i/o5 i/o6 i/o7 we# a17 a16 a15 a14 a13 cc ss a5 a6 a7 oe# ub# lb# i/o15 i/o14 i/o13 i/o12 v v i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 a12 cc ss (top view) 44-pin tsop pin description pin na me func tion a0 to a17 address input i/o0 to i/o15 data input/output cs# ( cs ) c h i p s e l e c t oe# ( oe ) o u t p u t e n a b l e we# ( we ) w r i t e e n a b l e lb# ( lb ) low er by te select ub# ( ub ) upper by te select v cc p o w e r supply v ss g r o u n d n c n o c o n n e c t i o n rev.1.00, may . 24. 2007, page 2 of 12
r1lv0414d series block diagram ? i/o0 i/o15 we# oe# a0 a1 a2 a4 a17 v v cc ss row decoder memory matrix 2,048 x 2,048 column i/o column decoder input data control control logic a5 a13 a7 a8 a9 a10 a11 a12 a6 a14 a15 a16 cs# lb# ub# a3 lsb msb lsb msb rev.1.00, may . 24. 2007, page 3 of 12
r1lv0414d series operation table cs# we# oe# ub# lb# i/o0 to i/o7 i/o8 to i/o15 operation h h i g h - z high-z standby h h high-z high-z standby l h l l l d o u t d o u t r e a d l h l h l d o u t high-z low er by t e r e a d l h l l h high-z d o u t upper by t e r e a d l l l l d i n d i n w r i t e l l h l din high-z low er by te w r ite l l l h high-z din upper by te w r ite l h h h i g h - z high-z o u t p u t d i s a b l e note: h: v ih , l: v il , : v ih or v il absolute maximum ratings p a r a m e t e r s y m b o l v a l u e u n i t pow e r supply voltage relative to v ss v cc ? 0.5 to +4.6 v t e rminal voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0 . 3 * 2 v pow e r dissipation p t 0 . 7 w operating temperature t opr ? 40 to + 85 c storage temperature range t s tg ? 65 to + 150 c storage temperature range under bias t b ias ? 40 to + 85 c notes: 1. v t min: ? 3.0 v for pulse half-w i dth 30 ns. 2. maximum voltage is + 4 .6 v. dc operating conditions pa ra me te r s y m b o l m i n ty p ma x u n i t note supply voltage v cc 2 . 7 3 . 0 3 . 6 v v ss 0 0 0 v input high voltage v ih 2 . 2 v cc + 0.3 v input low voltage v il ? 0.3 0 . 6 v 1 ambient temperature range t a ? 40 + 85 c note: 1. v il min: ? 3.0 v for pulse half-w i dth 30 ns. rev.1.00, may . 24. 2007, page 4 of 12
r1lv0414d series dc characteristics pa ra me te r s y mbol m i n ty p ma x u nit t e s t c onditions input leakage current | i li | 1 a vin = v ss to v cc output leakage current | i lo | 1 a cs# = v ih or oe# = v ih or w e # = v il o r lb# = ub# = v ih , v i/o = v ss to v cc operating current i cc 20 ma cs# = v il , others = v ih /v il , i i/o = 0 ma average operating current i cc1 25 ma min. cy cle, duty = 100%, i i/o = 0 ma, cs# = v il , others = v ih /v il i cc2 5 ma cy cle time = 1 s, duty = 100%, i i/o = 0 ma, cs# 0.2 v, v ih v cc ? 0.2 v, v il 0.2 v standby current i sb 0.1 * 1 0.3 ma cs# = v ih to +85 c i sb1 1 0 a to +70 c i sb1 8 a to +40 c i sb1 3 a ? 5si to +25 c i sb1 1 * 1 2 . 5 a to +85 c i sb1 2 0 a to +70 c i sb1 1 6 a to +40 c i sb1 1 0 a standby current ? 7li to +25 c i sb1 1 * 1 1 0 a vin 0 v (1) cs# v cc ? 0.2 v (2) lb# = ub# v cc ? 0.2 v, c s # 0.2 v average values output high voltage v oh 2 . 4 ? ? v i oh = ? 1 ma v oh2 v cc ? 0.2 ? ? v i oh = ? 100 a output low voltage v ol ? ? 0 . 4 v i ol = 2 ma v ol2 ? ? 0 . 2 v i ol = 100 a notes: 1. t y pical values are at v cc = 3 . 0 v, t a = +2 5 c and specified loadi ng, and not guaranteed. capacitance (ta = +25 c , f = 1.0 m h z) pa ra me te r s y m b o l m i n ty p ma x u n i t te s t c onditions note input capacitance cin 8 pf vin = 0 v 1 input/output capacitance c i/o 1 0 p f v i/o = 0 v 1 note: 1. t h is parameter is sampled and not 100 % tested. rev.1.00, may . 24. 2007, page 5 of 12
r1lv0414d series ac characteristics (ta = ? 40 t o +85 c, v cc = 2.7 v t o 3.6 v) test conditions ? input pul se l e vel s : v il = 0.4 v, v ih = 2.4 v ? input ri se and fal l t i m e: 5 ns input / out put t i m i ng reference l e vel s : 1.4 v ? out put l o ad: see fi gures (incl udi ng scope and ji g) 50 pf dout rl=500 1.4 v output load read cy cle r1l v 0414d - 5 s i - 7 l i p a r a m e t e r sy m b o l m i n m a x m i n m a x u n i t n o t e s read cy cle time t rc 5 5 7 0 n s address access time t aa 5 5 7 0 n s chip select access time t ac s 5 5 7 0 n s output enable to output valid t oe 3 5 4 0 n s output hold from address change t oh 1 0 1 0 n s lb#, ub# access time t ba 5 5 7 0 n s chip select to output in low - z t cl z 1 0 1 0 n s 2 , 3 lb#, ub# disable to low - z t blz 5 5 n s 2 , 3 output enable to output in low - z t olz 5 5 n s 2 , 3 chip deselect to output in high-z t chz 0 2 0 0 2 5 n s 1 , 2 , 3 lb#, ub# disable to high-z t bh z 0 2 0 0 2 5 n s 1 , 2 , 3 output disable to output in high-z t ohz 0 2 0 0 2 5 n s 1 , 2 , 3 rev.1.00, may . 24. 2007, page 6 of 12
r1lv0414d series write cy cle r1l v 0414d - 5 s i - 7 l i p a r a m e t e r sy m b o l m i n m a x m i n m a x u n i t n o t e s write cy cle time t wc 5 5 ? 7 0 ? n s address valid to end of w r ite t aw 5 0 ? 6 0 ? n s chip selection to end of w r ite t cw 5 0 ? 6 0 ? n s 5 w r ite pulse w i dth t wp 4 0 ? 5 0 ? n s 4 lb#, ub# valid to end of w r ite t bw 5 0 ? 5 5 ? n s address setup time t as 0 ? 0 ? n s 6 write recovery time t wr 0 ? 0 ? n s 7 data to w r ite time overlap t dw 2 5 ? 3 0 ? n s data hold from w r ite time t dh 0 ? 0 ? n s output active from end of w r ite t ow 5 ? 5 ? n s 2 output disable to output in high-z t ohz 0 2 0 0 2 5 n s 1 , 2 , 3 w r ite to output in high-z t wh z 0 2 0 0 2 5 n s 1 , 2 notes: 1. t chz , t ohz , t wh z and t bh z are defined as the time at w h ich the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. t h is parameter is sampled and not 100 % tested. 3. at any given temper ature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a w r ite occurs during the overlap of a low cs#, a low w e # and a low lb# or a low ub#. a w r ite begins at the latest transition among cs# going low , w e # going low and lb# going low or ub# going low . a w r ite ends at the earliest transition among cs# going high, w e # going high and lb# going high or ub# going high. t wp is measured from the beginning of w r ite to the end of w r ite. 5. t cw is measured from cs# going low to the end of w r ite. 6. t as is measured from the address va lid to the beginning of w r ite. 7. t wr is measured from the earlier of cs# or w e # going high to the end of w r ite cy cle. rev.1.00, may . 24. 2007, page 7 of 12
r1lv0414d series timing waveform read timing wav e form (we# = v ih ) t aa t acs t clz t blz t ba t oh t rc valid data address dout valid address high impedance cs# lb#, ub# oe# * 1, 2, 3 * 1, 2, 3 * 2, 3 * 2, 3 * 1, 2, 3 t olz * 2, 3 t oe t chz t bhz t ohz rev.1.00, may . 24. 2007, page 8 of 12
r1lv0414d series write tim i ng wav e form (1) (we# clock) address we# t wc t aw t wp * 4 t wr * 7 t cw * 5 t bw t as * 6 t ow * 2 t whz * 1, 2 t dw t dh valid address valid data cs# lb#, ub# dout din high impedance rev.1.00, may . 24. 2007, page 9 of 12
r1lv0414d series write tim i ng wav e form (2) (cs # clock, oe # = v ih ) address we# t wc t aw t wp * 4 t wr * 7 t cw * 5 t bw t as * 6 t dw t dh valid address valid data lb#, ub# dout din high impedance cs# address we# t wc t aw t wp * 4 t cw * 5 t bw t wr * 7 t dw t dh valid address valid data lb#, ub# dout din high impedance cs# t as * 6 write tim i ng wav e form (3) (lb#, ub# clock, oe# = v ih ) rev.1.00, may . 24. 2007, page 10 of 12
r1lv0414d series low v cc data retention characteristics (ta = ? 40 t o +85 c) pa ra me te r s y m b o l min t y p ma x u nit t e s t c onditions v cc for data retention v dr 2 v vin 0v (1) cs# v cc ? 0.2 v or (2) lb# = ub# v cc ? 0.2 v, cs# 0.2 v to +85 c i ccdr 1 0 a to +70 c i ccdr 8 a to +40 c i ccdr 3 a ? 5si to +25 c i ccdr 1 * 1 2 . 5 a to +85 c i ccdr 2 0 a to +70 c i ccdr 1 6 a to +40 c i ccdr 1 0 a data retention current ? 7li to +25 c i ccdr 1 * 1 1 0 a v cc = 3.0 v, vin 0v (1) cs# v cc ? 0.2 v or (2) lb# = ub# v cc ? 0.2 v, cs# 0.2 v average values chip deselect to data retention time t cdr 0 ns see retention w a veform operation recovery time t r 5 m s note: 1. t y pical values are at v cc = 3 . 0 v, t a = +2 5 c and specified loadi ng, and not guaranteed. rev.1.00, may . 24. 2007, page 11 of 12
r1lv0414d series rev.1.00, may . 24. 2007, page 12 of 12 low v cc data retention tim i ng wav e form (1) (cs# controlled) cc v 2.2 v 2.7 v 0 v cs# t cdr t r cs# v ? 0.2 v cc low v cc data retention tim i ng wav e form (2) (lb#, ub# controlled)
revision history r1lv0414d series data sheet contents of modification rev. date page description 0.01 dec. 25, 2006 ?
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